Register Descriptions; Standby Control Register (Sbycr) - Renesas H8S Series Hardware Manual

Section 20 Power-Down Modes
20.1

Register Descriptions

Registers related to the power down mode are shown below. For details on the system clock
control register (SCKCR), refer to section 19.1.1, System Clock Control Register (SCKCR). For
details on register addresses and register states during each process, refer to appendix A, On-Chip
I/O Register.
• System clock control register (SCKCR)

• Standby control register (SBYCR)

• Module stop control register A (MSTPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)
20.1.1 Standby Control Register (SBYCR)
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Bit Bit Name
7 SSBY
Rev. 6.00 Mar 15, 2006 page 494 of 570
REJ09B0211-0600
Initial Value R/W
0 R/W
Description
Software Standby
This bit specifies the transition mode after executing
the SLEEP instruction
0: Shifts to sleep mode when the SLEEP instruction
is executed
1: Shifts to software standby mode when the SLEEP
instruction is executed
This bit does not change when clearing the software
standby mode by using external interrupts and
shifting to normal operation. This bit should be
written with 0 when clearing.