Register Descriptions; Standby Control Register (Sbycr) - Renesas H8S/2368 Series Hardware Manual

22.1

Register Descriptions

The registers relating to the power-down mode are shown below. For details on the system clock
control register (SCKCR), refer to section 21.1.1, System Clock Control Register (SCKCR).
• System clock control register (SCKCR)

• Standby control register (SBYCR)

• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)
• Extension module stop control register H (EXMSTPCRH)
• Extension module stop control register L (EXMSTPCRL)
22.1.1 Standby Control Register (SBYCR)
SBYCR performs software standby mode control.
Bit Bit Name
7 SSBY
6 OPE
Rev. 2.00, 05/03, page 686 of 820
Initial Value R/W
0 R/W
1 R/W
Description
Software Standby
This bit specifies the transition mode after
executing the SLEEP instruction
0: Shifts to sleep mode after the SLEEP instruction
is executed
1: Shifts to software standby mode after the SLEEP
instruction is executed
This bit does not change when clearing the
software standby mode by using external interrupts
and shifting to normal operation. This bit should be
written 0 when clearing.
Output Port Enable
Specifies whether the output of the address bus
and bus control signals (CS0 to CS7, AS, RD,
HWR, LWR, UCAS*, LCAS*) is retained or set to
the high-impedance state in software standby
mode.
0: In software standby mode, address bus and bus
control signals are high-impedance
1: In software standby mode, address bus and bus
control signals retain output state