Register Descriptions; Standby Control Register (Sbycr) - Renesas H8S/2100 Series Hardware Manual

Section 26 Power-Down Modes
26.1

Register Descriptions

Power-down modes are controlled by the following registers. To access SBYCR, LPWRCR,
SYSCR2, MSTPCRH, and MSTPCRL the FLSHE bit in the serial timer control register (STCR)
must be cleared to 0. For details on STCR, see section 3.2.3, Serial Timer Control Register
(STCR). For details on the PSS bit in TSCR_1 (WDT_1), see TCSR_1 in section 12.3.5, Timer
Control/Status Register (TCSR).
Table 26.1 Register Configuration
Register Name
Standby control register
Low power control register
Module stop control register H MSTPCRH
Module stop control register L MSTPCRL
Module stop control register A MSTPCRA
Module stop control register B MSTPCRB
26.1.1

Standby Control Register (SBYCR)

SBYCR controls power-down modes.
Bit Bit Name
7 SSBY
Rev. 1.00 May 09, 2008 Page 810 of 954
REJ09B0462-0100
Abbreviation
SBYCR
LPWRCR
Initial
Value R/W
0 R/W
R/W Initial Value Address
R/W H'00
R/W H'00
R/W H'3F
R/W H'FF
R/W H'FC
R/W H'FF
Description
Software Standby
Specifies the operating mode to be entered after
executing the SLEEP instruction.
When the SLEEP instruction is executed in high-
speed mode or medium-speed mode:
0: Shifts to sleep mode
1: Shifts to software standby mode or watch mode
Note that the SSBY bit is not changed even if a mode
transition is made by an interrupt.
Data Bus
Width
H'FF84 8
H'FF85 8
H'FF86 8
H'FF87 8
H'FE7E 8
H'FE7F 8