Transmit Shift Register (Tsr); Serial Mode Register (Smr) - Renesas H8S/2368 Series Hardware Manual

14.3.4

Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot
be directly accessed by the CPU.
14.3.5

Serial Mode Register (SMR)

SMR is used to set the SCI's serial transfer format and select the on-chip baud rate generator clock
source.
Some bit functions of SMR differ in normal serial communication interface mode and Smart Card
interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR is 0)
Bit Bit Name
7 C/A
6 CHR
5 PE
4 O/E
Rev. 2.00, 05/03, page 512 of 820
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is
fixed and the MSB (bit 7) of TDR is not
transmitted in transmission.
In clocked synchronous mode, a fixed data length
of 8 bits is used.
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. For a multiprocessor
format, parity bit addition and checking are not
performed regardless of the PE bit setting.
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.