Serial Mode Register (Smr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.2.5

Serial Mode Register (SMR)

Note: • Some bits in SMR have different functions in serial communications interface mode and smart card interface
mode.
(1) Serial Communications Interface Mode (SMIF in SCMR = 0)
b7 b6
CM CHR
Value after reset: 0 0
Bit Symbol Bit Name
b1, b0 CKS[1:0] Clock Select
b2 MP Multi-Processor Mode
b3 STOP Stop Bit Length
b4 PM Parity Mode
b5 PE Parity Enable
b6 CHR Character Length
b7 CM Communications Mode
Note 1. n is the decimal notation of the value of n in BRR (see section 15.2.9, Bit Rate Register (BRR)).
Note 2. In clock synchronous mode, this bit setting is invalid and a fixed data length of 8 bits is used.
Note 3. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission.
Note 4. Writable only when TE in SCR = 0 and RE in SCR = 0 (both serial transmission and reception are disabled).
CKS[1:0] Bits (Clock Select)
These bits select the clock source for the on-chip baud rate generator.
For the relation between the settings of these bits and the baud rate, see section 15.2.9, Bit Rate Register (BRR).
MP Bit (Multi-Processor Mode)
Disables/enables the multi-processor communications function. The settings of the PE bit and PM bit are invalid in
multi-processor mode.
STOP Bit (Stop Bit Length)
Selects the stop bit length in transmission.
In reception, only the first stop bit is checked regardless of this bit setting. If the second stop bit is 0, it is treated as the
start bit of the next transmit frame.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b5 b4 b3 b2
PE PM STOP MP
0 0 0 0
b1 b0
CKS[1:0]
0 0
Description
b1 b0
1
0 0: P1φ clock (n = 0)*
1
0 1: P1φ/4 clock (n = 1)*
1
1 0: P1φ/16 clock (n = 2)*
1
1 1: P1φ/64 clock (n = 3)*
(Valid only in asynchronous mode)
0: Multi-processor communications function is disabled
1: Multi-processor communications function is enabled
(Valid only in asynchronous mode)
0: 1 stop bit
1: 2 stop bits
(Valid only when the PE bit is 1 in asynchronous mode)
0: Selects even parity
1: Selects odd parity
(Valid only in asynchronous mode)
• When transmitting
0: Parity bit addition is not performed
1: The parity bit is added
• When receiving
0: Parity bit checking is not performed
1: The parity bit is checked
(Valid only in asynchronous mode)
0: Selects 8 bits as the data length*
1: Selects 7 bits as the data length*
0: Asynchronous mode
1: Clock synchronous mode
15. Serial Communications Interface
2
3
R/W
4
R/W*
4
R/W*
4
R/W*
4
R/W*
4
R/W*
4
R/W*
4
R/W*
15-5