Transmit Data Register (Tdr); Serial Mode Register (Smr) - Renesas H8S Series Hardware Manual

14.2.4

Transmit Data Register (TDR)

Bit : 7
Initial value : 1
R/W : R/W
TDR is an 8-bit register that stores data for serial transmission.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial
transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial
transmission of the data in TSR.
TDR can be read or written to by the CPU at all times.
TDR is initialized to H'FF by a reset, and in standby mode or module stop mode.
14.2.5

Serial Mode Register (SMR)

Bit : 7
C/A
Initial value : 0
R/W : R/W
SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source.
SMR can be read or written to by the CPU at all times.
SMR is initialized to H'00 by a reset, and by putting the device in standby mode or module stop mode. In the H8S/2398,
H8S/2394, H8S/2392, and H8S/2390, however, the value in SMR is initialized to H'00 by a reset, or in hardware standby
mode, but SMR retains its current state when the device enters software standby mode or module stop mode.
Bit 7—Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating
mode.
Bit 7
C/A
0
1
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous
mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR
0
1
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between
LSB-first or MSB-first transfer.
Rev.6.00 Oct.28.2004 page 470 of 1016
REJ09B0138-0600H
6 5
1 1
R/W R/W
6 5
CHR PE
0 0
R/W R/W
Description
Asynchronous mode
Clocked synchronous mode
Description
8-bit data
7-bit data*
4 3 2
1 1 1
R/W R/W R/W
4 3 2
O/E STOP MP
0 0 0
R/W R/W R/W
1 0
1 1
R/W R/W
1 0
CKS1 CKS0
0 0
R/W R/W
(Initial value)
(Initial value)