Serial Control Register (Scr) - Renesas H8S/2437 Hardware Manual

16.3.6

Serial Control Register (SCR)

SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, see section
16.7, Interrupt Sources.
Bit Bit Name
7 TIE
6 RIE
5 TE
4 RE
3 MPIE
2 TEIE
Initial Value R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, a TXI interrupt request is
enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of
the RDRF, FER, and ORER status flags in SSR is
disabled. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, see section 16.5, Multiprocessor
Communication Function.
Transmit End Interrupt Enable
When this bit is set to 1, a TEI interrupt request is
enabled.
Rev. 1.00, 09/03, page 431 of 704