Receive Shift Register (Rsr); Receive Data Register (Rdr); Transmit Data Register (Tdr); Transmit Shift Register (Tsr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
15.2.1

Receive Shift Register (RSR)

RSR is a shift register which is used to receive serial data input from the RXDn pin and converts it into parallel data.
When one frame of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
15.2.2

Receive Data Register (RDR)

b7 b6
0 0
Value after reset:
RDR is an 8-bit register that stores receive data.
When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is
stored. This allows RSR to receive the next data.
Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed.
Only read RDR once after each instance of the receive data full interrupt (RXI). Note that if next one frame of data is
received before reading receive data from RDR, an overrun error occurs.
RDR cannot be written to by the CPU.
15.2.3

Transmit Data Register (TDR)

b7 b6
Value after reset: 1 1
TDR is an 8-bit register that stores transmit data.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission.
The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has
already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue
transmission.
The CPU is able to read from or write to TDR at any time. Only write data for transmission to TDR once after each
instance of the transmit data empty interrupt (TXI).
15.2.4

Transmit Shift Register (TSR)

TSR is a shift register that transmits serial data.
To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, and then sends
the data to the TXDn pin.
TSR cannot be directly accessed by the CPU.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
b5 b4 b3 b2
0 0 0 0
b5 b4 b3 b2
1 1 1 1
b1 b0
0 0
b1 b0
1 1
15. Serial Communications Interface
15-4