Refresh Timer Control/Status Register (Rtcsr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.4.5

Refresh Timer Control/Status Register (RTCSR)

RTCSR specifies various items about refresh for SDRAM.
When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection.
The phase of the clock for incrementing the count in the refresh timer counter (RTCNT) is adjusted only by a power-on
reset. Note that there is an error in the time until the compare match flag is set for the first time after the timer is started
with the CKS[2:0] bits being set to a value other than B'000.
Bit: 31
-
Initial value:
0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
31 to 8 ―
7 CMF
6 CMIE
5 to 3 CKS[2:0]
2 to 0 RRC[2:0]
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
0 R/W
0 R/W
000 R/W
000 R/W
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- - CMF CMIE
0 0 0 0 0
R R R/W R/W R/W
Description
Reserved
These bits are always read as 0.
Compare Match Flag
Indicates that a compare match occurs between the refresh timer counter
(RTCNT) and refresh time constant register (RTCOR). This bit is set or
cleared in the following conditions.
0: Clearing condition: When 0 is written in CMF after reading out RTCSR
during CMF = 1.
1: Setting condition: When the condition RTCNT = RTCOR is satisfied.
Compare Match Interrupt Enable
Enables or disables CMF interrupt requests when the CMF bit in RTCSR
is set to 1.
0: Disables CMF interrupt requests.
1: Enables CMF interrupt requests.
Clock Select
Select the clock input to count-up the refresh timer counter (RTCNT).
000: Stop the counting-up
001: CKIOφ/4
010: CKIOφ/16
011: CKIOφ/64
100: CKIOφ/256
101: CKIOφ/1024
110: CKIOφ/2048
111: CKIOφ/4096
Refresh Count
Specify the number of continuous refresh cycles, when the refresh request
occurs after the coincidence of the values of the refresh timer counter
(RTCNT) and the refresh time constant register (RTCOR). These bits can
make the period of occurrence of refresh long.
000: 1 time
001: 2 times
010: 4 times
011: 6 times
100: 8 times
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
8. Bus State Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
CKS[2:0] RRC[2:0]
0 0 0 0 0
R/W R/W R/W R/W R/W
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