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Section 7 Refresh Controller
7.2.2
Refresh Timer Control/Status Register (RTMCSR)
RTMCSR is an 8-bit readable/writable register that selects the clock source for RTCNT. It also
enables or disables interrupt requests when the refresh controller is used as an interval timer.
Bit
7
CMF
Initial value
0
Read/Write
R/(W)
Compare match flag
Status flag indicating that RTCNT has matched RTCOR
Note:
Only 0 can be written, to clear the flag.
*
Bits 7 and 6 are initialized by a reset and in standby mode. Bits 5 to 3 are initialized by a reset and
in hardware standby mode, but retain their previous values on transition to software standby mode.
Bit 7—Compare Match Flag (CMF): This status flag indicates that the RTCNT and RTCOR
values have matched.
Bit 7: CMF
Description
0
[Clearing condition]
Cleared by reading CMF when CMF = 1, then writing 0 in CMF
1
[Setting condition]
When RTCNT = RTCOR
Rev. 3.00 Mar 21, 2006 page 152 of 814
REJ09B0302-0300
6
5
CMIE
CKS2
0
0
R/W
R/W
*
Clock select 2 to 0
These bits select an
internal clock source
for input to RTCNT
Compare match interrupt enable
Enables or disables the CMI interrupt requested by CMF
4
3
CKS1
CKS0
0
0
R/W
R/W
2
1
0
—
—
—
1
1
1
—
—
—
Reserved bits
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