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(a) Read timing (SDRAM access)
BUSCLK (output)
A0-A25 (output)
BCYSTZ (output)
Note
CSZn
(output)
SDRASZ (output)
SDCASZ (output)
SDWEZ (output)
DQM0-DQM3 (output)
D0-D31 (I/O)
< t
SDCKE (output)
Note
n = 1, 3, 4, 6
Remarks 1.
Number of waits inserted by BCW1n and BCW0n bits of the SCRn register (TBCW)
2.
Broken lines indicate high impedance.
CHAPTER 1 PRODUCT SPECIFCATIONS
Figure 1-9. Read Timing (SDRAM Access)
TW
TACT
TBCW
< t
>
< t
>
< t
>
D KA
DKA
DKA
< t
>
< t
>
DKBC
DKBC
< t
>
DKCS
< t
>
< t
>
DKRAS
DKRAS
>
DKCKE
User's Manual A19069EJ2V0UM
TREAD
TLATE
TLATE
< t
>
< t
>
DKCAS
DKC AS
< t
>
D KDQM
< t
>
SKDRM
< t
>
D KA
< t
>
DKBC
< t
>
D KCS
< t
>
DKWE
< t
>
DKDQM
< t
>
HKDRM
< t
>
DKCKE
27
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