I2C Programmable Input Glitch Filter Register (I2Cx_Flt) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Field
7 General Call Address Enable
GCAEN
Enables general call address.
0 Disabled
1 Enabled
6 Address Extension
ADEXT
Controls the number of bits used for the slave address.
0 7-bit address scheme
1 10-bit address scheme
5 High Drive Select
HDRS
Controls the drive capability of the I2C pads.
0 Normal drive mode
1 High drive mode
4 Slave Baud Rate Control
SBRC
Enables independent slave mode baud rate at maximum frequency, which forces clock stretching on SCL
in very fast I2C modes. To a slave, an example of a "very fast" mode is when the master transfers at 40
kbit/s but the slave can capture the master's data at only 10 kbit/s.
0 The slave baud rate follows the master baud rate and clock stretching may occur
1 Slave baud rate is independent of the master baud rate
3 Range Address Matching Enable
RMEN
This bit controls the slave address matching for addresses between the values of the A1 and RA registers.
When this bit is set, a slave address matching occurs for any address greater than the value of the A1
register and less than or equal to the value of the RA register.
0 Range mode disabled. No address matching occurs for an address within the range of values of the
A1 and RA registers.
1 Range mode enabled. Address matching occurs when a slave receives an address within the range of
values of the A1 and RA registers.
AD[10:8] Slave Address
Contains the upper three bits of the slave address in the 10-bit address scheme. This field is valid only
while the ADEXT bit is set.

36.4.7 I2C Programmable Input Glitch Filter Register (I2Cx_FLT)

Address: Base address + 6h offset
Bit 7
Read
SHEN
Write
Reset
0
Freescale Semiconductor, Inc.
I2Cx_C2 field descriptions
6 5
STOPF STARTF
SSIE
w1c
0 0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Chapter 36 Inter-Integrated Circuit (I2C)
Description
4 3
w1c
0 0
2 1
FLT
0 0
0
0
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