Functional Details - NXP Semiconductors freescale KV4 Series Reference Manual

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Functional Description

37.5.2 Functional Details

This section describes the implementation of various sections of the PWM in greater

The following figure is a high-level block diagram of output PWM generation.

PWM_EXT_SYNC

PWM_EXT_FORCE

PWM Generation

Output Triggers

Figure 37-233. High-Level Output PWM Generation Block Diagram

37.5.2.1 PWM Clocking

Figure 37-234

shows the logic used to generate the main counter clock. Each submodule

can select between three clock signals: the IPBus clock, EXT_CLK, and AUX_CLK. The

EXT_CLK goes to all of the submodules. The AUX_CLK signal is broadcast from

submodule0 and can be selected as the clock source by other submodules so that the 8-bit

prescaler and MCTRL[RUN] from submodule0 can control all of the submodules.

I PB us clock

AUX_CLK input

(from submod0)

Figure 37-234. Clocking Block Diagram for Each PWM Submodule

Force Out Logic

Insertion Logic

KV4x Reference Manual, Rev. 2, 02/2015

Fault Protection

16 bit counter

Output Logic

AUX_CLK output

(from submod0 only)

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