Arm® Cortex®-M4 Core Modules - NXP Semiconductors freescale KV4 Series Reference Manual

Module Functional Categories
Table 2-1. Module functional categories (continued)
Module category
Security
Analog
Timers
Communications
Human-Machine Interfaces (HMI)
2.2.1 ARM® Cortex®-M4 Core Modules
The following core modules are available on this device.
Module
ARM Cortex-M4
Floating Point Unit (FPU)
NVIC
AWIC
64
• Cyclic Redundancy Check module for error detection
• Two 12-bit analog-to-digital converters (ADC) with 240 ns conversion time
• Four high speed comparators (CMP)
• Digital-to-analog converter (DAC)
• Two Programmable Delay Blocks (PDB)
• Three FlexTimers (FTM)
• Pulse Width Modulator (eFlexPWM)
• Periodic interrupt timer (PIT)
• Quadrature Encoder/Decoder (ENC)
• Low-Power Timer (LPTMR)
• Two Flex Controller Area Network (FlexCAN)
• Serial Peripheral Interface (SPI)
• Inter-integrated circuit (I
• Two Universal Asynchronous Receiver/Transmitters (UART)
• General purpose input/output controller
Table 2-2. Core modules
The ARM® Cortex®-M4 is the newest member of the Cortex M Series of
processors targeting microcontroller cores focused on very cost sensitive,
deterministic, interrupt driven environments. The Cortex M4 processor is based on
the ARMv7 Architecture and Thumb®-2 ISA and is upward compatible with the
Cortex M3, Cortex M1, and Cortex M0 architectures. Cortex M4 improvements
include an ARMv7 Thumb-2 DSP (ported from the ARMv7-A/R profile
architectures) providing 32-bit instructions with SIMD (single instruction multiple
data) DSP style multiply-accumulates and saturating arithmetic.
A single-precision floating point unit (FPU) that is compliant to the IEEE Standard
for Floating-Point Arithmetic (IEEE 754).
The ARMv7-M exception model and nested-vectored interrupt controller (NVIC)
implement a relocatable vector table supporting many external interrupts, a single
non-maskable interrupt (NMI), and priority levels.
The NVIC replaces shadow registers with equivalent system and simplified
programmability. The NVIC contains the address of the function to execute for a
particular handler. The address is fetched via the instruction port allowing parallel
register stacking and look-up. The first sixteen entries are allocated to ARM
internal sources with the others mapping to MCU-defined interrupts.
The primary function of the Asynchronous Wake-up Interrupt Controller (AWIC) is
to detect asynchronous wake-up events in stop modes and signal to clock control
logic to resume system clocking. After clock restart, the NVIC observes the
pending interrupt and performs the normal interrupt or event processing.
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
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