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Memory map and register definition
31.4 Memory map and register definition
Absolute
address
(hex)
4004_0000
Low Power Timer Control Status Register (LPTMR0_CSR)
4004_0004
Low Power Timer Prescale Register (LPTMR0_PSR)
4004_0008
Low Power Timer Compare Register (LPTMR0_CMR)
4004_000C Low Power Timer Counter Register (LPTMR0_CNR)
31.4.1 Low Power Timer Control Status Register (LPTMRx_CSR)
Address: 4004_0000h base + 0h offset = 4004_0000h
Bit
31
30
29
R
W
Reset
0
0
0
15
14
13
Bit
R
W
Reset
0
0
0
Field
31–8
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
7
Timer Compare Flag
TCF
TCF is set when the LPTMR is enabled and the CNR equals the CMR and increments. TCF is cleared
when the LPTMR is disabled or a logic 1 is written to it.
0
The value of CNR is not equal to CMR and increments.
1
The value of CNR is equal to CMR and increments.
6
Timer Interrupt Enable
TIE
When TIE is set, the LPTMR Interrupt is generated whenever TCF is also set.
0
Timer interrupt disabled.
1
Timer interrupt enabled.
5–4
Timer Pin Select
TPS
504
LPTMR memory map
Register name
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
0
LPTMRx_CSR field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
Width
Access
(in bits)
32
32
32
32
24
23
22
21
0
0
0
0
0
8
7
6
5
TCF
TIE
TPS
w1c
0
0
0
0
Description
Section/
Reset value
page
R/W
0000_0000h
31.4.1/504
R/W
0000_0000h
31.4.2/505
R/W
0000_0000h
31.4.3/507
R/W
0000_0000h
31.4.4/507
20
19
18
17
0
0
0
0
4
3
2
1
TPP
TFC
TMS
0
0
0
0
Freescale Semiconductor, Inc.
16
0
0
TEN
0
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