Pseudo-Code Example - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

Initialization/application information

1. Update the Control Register 1 (SPIx_C1) to enable the SPI and to control interrupt

enables. This register also sets the SPI as master or slave, determines clock phase and

polarity, and configures the main SPI options.

2. Update the Control Register 2 (SPIx_C2) to enable additional SPI functions such as

the SPI match interrupt feature, the master mode-fault function, and bidirectional

mode output as well as to control 8- or 16-bit mode selection and other optional

3. Update the Baud Rate Register (SPIx_BR) to set the prescaler and bit rate divisor for

an SPI master.

4. Update the Hardware Match Register (SPIx_MH:SPIx_ML) with the value to be

compared to the receive data register for triggering an interrupt if hardware match

interrupts are enabled.

5. In the master, read SPIx_S while S[SPTEF] = 1, and then write to the transmit data

35.6.2 Pseudo-Code Example

In this example, the SPI module is set up for master mode with only hardware match

interrupts enabled. The SPI runs in 16-bit mode at a maximum baud rate of SPI module

clock divided by 2. Clock phase and polarity are set for an active-high SPI clock where

the first edge on SPSCK occurs at the start of the first cycle of a data transfer.

SPIx_C1=0x54(%01010100)

SPIx_C2 = 0xC0(%11000000)

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KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Disables receive and mode fault interrupts

Enables the SPI system

Disables SPI transmit interrupts

Sets the SPI module as a master SPI device

Configures SPI clock as active-high

First edge on SPSCK at start of first data transfer cycle

Determines SS pin function when mode fault enabled

SPI serial data transfers start with most significant bit

SPI hardware match interrupt enabled

Configures SPI for 16-bit mode

DMA request disabled

Disables mode fault function

Freescale Semiconductor, Inc.