Dma Operation; Resets; Low-Power Mode Operation - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Table of Contents

25.5.2 DMA operation

When DMA is enabled, DMA requests are generated instead of interrupt requests. The

DMA Done signal clears the DMA request.

The status register flags are still set and are cleared automatically when the DMA

During reset, the DAC is configured in the default mode and is disabled.

The following table shows the wait mode and the stop mode operation of the DAC

The assignment of module modes to core modes is chip-

specific. For module-to-core mode assignments, see the chapter

that describes how modules are configured.

Freescale Semiconductor, Inc.

Table 25-1. Modes of DAC data buffer operation

Table 25-2. Modes of operation

Modes of operation

The DAC will operate normally, if enabled.

If enabled, the DAC module continues to operate

in Normal Stop mode and the output voltage will

hold the value before stop.

In low-power stop modes, the DAC is fully

KL27 Sub-Family Reference Manual , Rev. 5, 01/2016

Chapter 25 12-bit Digital-to-Analog Converter (DAC)

be happened when DAC is not enabled for 1st data

conversion enable. But FIFO mode need to work at

buffer Enabled at DACC1[DACBFEN].

In FIFO mode, the DATA BUF will be organized as FIFO.