Low Voltage Detect Status And Control 1 Register (Pmc_Lvdsc1) - NXP Semiconductors MKL27Z128VFM4 Reference Manual

Memory map and register descriptions
15.5.1 Low Voltage Detect Status And Control 1 register
(PMC_LVDSC1)
This register contains status and control bits to support the low voltage detect function.
This register should be written during the reset initialization program to set the desired
controls even if the desired settings are the same as the reset settings.
While the device is in the very low power or low leakage modes, the LVD system is
disabled regardless of LVDSC1 settings. To protect systems that must have LVD always
on, configure the Power Mode Protection (PMPROT) register of the SMC module
(SMC_PMPROT) to disallow any very low power or low leakage modes from being
enabled.
See the device's data sheet for the exact LVD trip voltages.
The LVDV bits are reset solely on a POR Only event. The
register's other bits are reset on Chip Reset Not VLLS. For
more information about these reset types, refer to the Reset
section details.
Address: 4007_D000h base + 0h offset = 4007_D000h
Bit 7
Read LVDF
Write
Reset
0
Field
7 Low-Voltage Detect Flag
LVDF
This read-only status field indicates a low-voltage detect event.
0 Low-voltage event not detected
1 Low-voltage event detected
6 Low-Voltage Detect Acknowledge
LVDACK
This write-only field is used to acknowledge low voltage detection errors. Write 1 to clear LVDF. Reads
always return 0.
5 Low-Voltage Detect Interrupt Enable
LVDIE
Enables hardware interrupt requests for LVDF.
0 Hardware interrupt disabled (use polling)
1 Request a hardware interrupt when LVDF = 1
244
NOTE
6 5
0
LVDIE
LVDACK
0 0
PMC_LVDSC1 field descriptions
Table continues on the next page...
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
4 3
0
LVDRE
1 0
Description
2 1
LVDV
0 0
Freescale Semiconductor, Inc.
0
0