Table of Contents
Advertisement
Memory map and register definition
12.3.11 System Clock Gating Control Register 7 (SIM_SCGC7)
Address: 4004_7000h base + 1040h offset = 4004_8040h
Bit
31
30
29
R
W
Reset
0
0
0
Bit
15
14
13
R
W
Reset
0
0
0
Field
31–9
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
8
DMA Clock Gate Control
DMA
Controls the clock gate to the DMA module.
0
Clock disabled
1
Clock enabled
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
12.3.12 System Clock Divider Register 1 (SIM_CLKDIV1)
The CLKDIV1 register cannot be written to when the device is
in VLPR mode.
Reset value loaded during System Reset from
FTFA_FOPT[LPBOOT] (See
Address: 4004_7000h base + 1044h offset = 4004_8044h
Bit
31
30
29
28
27
26
R
OUTDIV1
W
*
*
*
*
0
0
Reset
* Notes:
•
OUTDIV1 field: The reset value depends on the FTFA_FOPT[LPBOOT]. It is loaded with 0000 (divide by 1), 0001 (divide by
2), 0011 (divide by 4, or 0111 (divide by 8).
162
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
0
SIM_SCGC7 field descriptions
25
24
23
22
21
20
19
18
0
OUTDIV4
0
0
0
0
0
0
0
0
KL27 Sub-Family Reference Manual , Rev. 5, 01/2016
24
23
22
21
0
0
0
0
0
8
7
6
5
DMA
1
0
0
0
Description
NOTE
NOTE
Table
6-2).
17
16
15
14
13
12
11
10
0
1
0
0
0
0
0
0
20
19
18
17
0
0
0
0
4
3
2
1
0
0
0
0
0
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
0
Freescale Semiconductor, Inc.
16
0
0
0
1
0
0
0
Advertisement
Table of Contents
