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Serial Host Interface (SHI, SHI_1)
•
Generate vectored interrupts separately for receive and transmit events, and update status bits
•
Generate a separate vectored interrupt for a receive exception
•
Generate a separate vectored interrupt for a bus error exception
•
Generate the clock signal (in master mode)
•
Trigger DMA interrupts to service the transmit and receive events
10.2
Serial Host Interface Internal Architecture
The DSP core views the SHI as a memory-mapped peripheral in the X data memory space. The DSP uses
the SHI as a normal memory-mapped peripheral using standard polling, interrupt programming
techniques, or DMA transfers. Memory mapping enables the DSP to communicate with the SHI registers
using standard instructions and addressing modes. In addition, the MOVEP instruction allows
interface-to-memory and memory-to-interface data transfers without going through an intermediate
register. The DMA controller can be used to service the receive or transmit data paths. The single master
configuration allows the DSP to directly connect to dumb peripheral devices; for that purpose, a
programmable baud-rate generator is included to generate the clock signal for serial transfers. The host
side invokes the SHI for communication and data transfers with the DSP through a shift register that can
be accessed serially, using either the I
diagram.
SCK/SCL
MISO/SDA
Pin
Control
MOSI/HA0
Logic
SS/HA2
HREQ
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
10-2
2
C or the SPI bus protocols.
Clock
Generator
Controller
Logic
Input/Output Shift Register
Slave Address
Recognition Unit
(SAR)
Figure 10-1. Serial Host Interface Block Diagram
Figure 10-1
shows the SHI block
HCKR
HCSR
HTX
(IOSR)
HRX
(FIFO)
HSAR
Legend:
24-Bit
DSP Global
Data Bus
DSP Global
DMA Data
Bus
Host-Accessible
DSP-Accessible
Freescale Semiconductor
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