Ddr And Ddr2 Sdram - Freescale Semiconductor MPC8358E Hardware Specificftion

DDR and DDR2 SDRAM

Table 13. QUICC Engine Block Operating Frequency Limitations (continued)
Interface
UART/async HDLC
BISYNC
USB
Notes:
1. The QUICC Engine module needs to run at a frequency higher than or equal to what is listed in this table.
2. 'F' is the actual interface operating frequency.
3. The bit rate limit is independent of the data bus width (that is, the same for serial, nibble, or octal interfaces).
4. TDM in high-speed mode for serial data interface.
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR and DDR2 SDRAM interface
of the MPC8360E/58E.
6.1 DDR and DDR2 SDRAM DC Electrical Characteristics
Table 14 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GV (typ) = 1.8 V
DD
Table 14. DDR2 SDRAM DC Electrical Characteristics for GV
Parameter/Condition
I/O supply voltage
I/O reference voltage
I/O termination voltage
Input high voltage
Input low voltage
Output leakage current
Output high current (V
OUT
Output low current (V = 0.280 V)
OUT
MV input leakage current
REF
MPC8360E/MPC8358E PowerQUICC II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 4
20
Interface Operating
Frequency (MHz)
3.68 (max internal ref
.
Symbol
GV
MV
REF
V
TT
V
IH
V
I
OZ
= 1.420 V) I
OH
I
OL
I
VREF
Max Interface Bit
Rate (Mbps)
115 (Kbps)
clock)
2 (max)
48 (ref clock)
Min
1.71
DD
0.49 × GV
DD
MV – 0.04
REF
MV + 0.125
REF
–0.3
IL
—
–13.4
13.4
—
Min QUICC Engine
Operating
1
Frequency (MHz)
20
2 20
12 96
(typ) = 1.8 V
DD
Max Unit
1.89
0.51 × GV
DD
MV + 0.04
REF
GV + 0.3
DD
MV – 0.125
REF
±10
—
—
±10
Freescale Semiconductor
Notes
—
—
—
Notes
V 1
V 2
V 3
V —
V —
μA
4
mA —
mA —
μA
—