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2.2.5
Reset Pin
Assert Reset to low and then high, to force a reset of the DSP cores.
description information.
Signal
State During
Type
Name
Reset
RESET Input
Input
2.2.6
Interrupt and Mode Control
The interrupt and mode control signals select the operating mode of the DSP cores as the cores come out
of hardware reset. After RESET is de-asserted, these inputs are used as hardware interrupt request lines.
Signal Name
Type
MODA0/IRQA
Input
PG5
Input, Output,
or
Disconnected
MODB0/IRQB
Input
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 2-7. Reset Pin
RESET is an active-low, Schmitt-trigger input. When asserted, the chip is placed in the Reset
state and the internal phase generator is reset. The Schmitt-trigger input allows a slowly rising
input (such as a capacitor charging) to reset the chip reliably. When the RESET signal is
de-asserted, the initial two cores operating modes are latched from the MODA0, MODB0,
MODC0, MODD0, MODA1, MODB1, MODC1, and MODD1 inputs. The RESET signal must be
asserted during power up. A stable EXTAL signal must be supplied while RESET is being
asserted. Uses an internal pull-up resistor.
Table 2-8. Interrupt and Mode Control
State During
Reset
MODA0
Mode Select A0/External Interrupt Request A
Input
MODA0/IRQA is an active-low Schmitt-trigger input, internally synchronized to
the DSP clock. MODA0/IRQA selects the initial Core-0 operating mode during
hardware reset, and becomes a two-core shared, level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal
instruction processing, This pin can also be programmed as GPIO.
MODA0, MODB0, MODC0, and MODD0 levels select one of 16 initial chip
operating modes, and are latched into the DSP Core-0's OMR when the RESET
signal is de-asserted. If the processor is in the stop standby state and the
MODA0/IRQA pin is pulled to GND, the processor will exit the stop state.
GPIO Port G5
When the MODA0/IRQA is configured as GPIO, this signal is individually
programmable as input, output, or internally disconnected; and can be controlled
by either of the two cores. Uses an internal pull-up resistor.
MODB0
Mode Select B0/External Interrupt Request B
Input
MODB0/IRQB is an active-low Schmitt-trigger input, internally synchronized to
the DSP clock. MODB0/IRQB selects the initial DSP Core-0 operating mode
during hardware reset and becomes a two-core shared, level-sensitive or
negative-edge-triggered, maskable interrupt request input during normal
instruction processing. This pin can also be programmed as GPIO.
MODA0, MODB0, MODC0, and MODD0 levels select one of 16 initial chip
operating modes, and are latched into the DSP Core-0's OMR when the RESET
signal is de-asserted.
Table 2-7
provides the Reset pin
Description
Description
Signal Descriptions
2-7
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