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1.4.7
Core Integration Modules (CIM, CIM_1)
Each DSP core has a Core Integration Module. Each core integration module includes a chip ID register,
DMA stall monitor function, and OnCE global data bus (GDB) register.
1.4.8
Sony/Philips Digital Interface (S/PDIF)
The Sony/Philips Digital Interface (S/PDIF) audio module is a transceiver that allows the DSP to receive
and transmit digital audio via this module. There is one S/PDIF in each DSP56724/DSP56725 device,
shared by the two DSP cores. The DSP provides a single S/PDIF receiver with four multiplexed inputs,
and one S/PDIF transmitter with two outputs. The S/PDIF module can also transmit and receive the
S/PDIF channel status (CS) and user (U) data. Not all S/PDIF pins are available on all packages.
1.4.9
Asynchronous Sample Rate Converter (ASRC)
Incoming audio data to the DSP can be received from various sources at different sampling rates. Outgoing
audio data from the DSP can have different sampling rates, and additionally, it can be associated with
output clocks that are asynchronous to the input clocks. The Asynchronous Sample Rate Converter
(ASRC) converts the sampling rate of a signal associated to an input clock into a signal associated to a
different output clock.
The ASRC supports concurrent sample rate conversion of up to 10 channels of about 120 dB THD+N. The
sample rate conversion of each channel is associated to a pair of incoming and outgoing sampling rates.
The ASRC supports up to three sampling rate pairs. Although there is only one ASRC in the
DSP56724/DSP56725 device (shared by the two DSP cores), the three sample rate pairs can be used by
both DSP cores at the same time. The ASRC is hard-coded and implemented as a co-processor, requiring
minimal CPU or DSP controller intervention.
1.4.10
External Memory Controller (EMC)
There is one EMC in each DSP56724 device, shared by the two DSP cores. Both cores can access external
memory using the EMC. (DSP56725 devices do not have an EMC.) The EMC provides a seamless
interface to many types of memory devices and peripherals over a shared address and data bus and
dedicated control signals. The memory controller in the EMC controls a parameterized number of memory
banks shared by a high performance SDRAM machine, a general-purpose chip-select machine (GPCM),
and up to three user-programmable machines (UPMs).
With external latching, it supports connections to synchronous DRAM (SDRAM), SRAM, EPROM, flash
EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals. Support signals for external address latch (LALE) allows multiplexing of address with data
lines in devices with strict pin count limitations.
1.4.11
Clock Generation Module (CGM)
The Clock Generation Module generates all clocks in the DSP56724/DSP56725 device; the output is a
series of gated clocks. The CGM uses a low jitter phase-locked loop (PLL). The PLL has a wide range of
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Introduction
1-7
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