Signals In Each Functional Group; Power; Ground - Freescale Semiconductor Symphony DSP56724 Reference Manual

2.2

Signals in Each Functional Group

2.2.1

Power

Power Name
PLLA_VDD PLL Power
PLLP_VDD The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance
PLLA1_VDD path to the 3.3 V
PLLP1_VDD
PLLD_VDD PLL Power
PLLD1_VDD The voltage (1.0 V) should be well-regulated and the input should be provided with an extremely low impedance
path to the 1.0 V
CORE_VDD Core Power
The voltage (1.0 V) should be well-regulated and the input should be provided with an extremely low impedance
path to the 1.0 V
IO_VDD I/O Power
The voltage (3.3 V) should be well-regulated and the input should be provided with an extremely low impedance
path to the 3.3 V
Timer I/O, and other IO signals. The user must provide adequate external decoupling capacitors.
2.2.2

Ground

Ground Name
PLLA_GND PLL Ground
PLLP_GND The PLL ground should be provided with an extremely low-impedance path to ground. The user must provide
PLLA1_GND adequate external decoupling capacitors.
PLLP1_GND
PLLD_GND PLL Ground
PLLD1_GND The PLL ground should be provided with an extremely low-impedance path to ground. The user must provide
adequate external decoupling capacitors.
CORE_GND Core Ground
The Core ground should be provided with an extremely low-impedance path to ground. This connection must
be tied externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors.
IO_GND I/O Ground
IO_GND is an isolated ground for the SHIs, ESAIs, Timer I/O and LIBU IO. This connection must be tied
externally to all other chip ground connections. The user must provide adequate external decoupling
capacitors.
GND Ground
This connection must be tied externally to all other chip ground connections. The user must provide adequate
external decoupling capacitors.
Symphony DSP56724/DSP56725 Multi-Core Audio Processors, Rev. 0
Freescale Semiconductor
Table 2-3. Power Pins
power rail. The user must provide adequate external decoupling capacitors.
DD
power rail. The user must provide adequate external decoupling capacitors.
DD
power rail. The user must provide adequate decoupling capacitors.
DD
power rail. This is an isolated power for the SHI, SHI_1, ESAI, ESAI_1, ESAI_2, ESAI_3,
DD
Table 2-4. Ground Pins
Description
Description
Signal Descriptions
2-5