Internal Bus; Access To Internal Address Space; Table 6.2 Number Of Access Cycles For On-Chip Memory Spaces; Table 6.3 Number Of Access Cycles For Registers Of On-Chip Peripheral Modules - Renesas H8SX/1520 Series Hardware Manual

6.5

Internal Bus

6.5.1

Access to Internal Address Space

The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space and
register space for the on-chip peripheral modules. The number of cycles necessary for access
differs according the space.
Table 6.2 shows the number of access cycles for each on-chip memory space.
Table 6.2
Access Space
On-chip ROM space
On-chip RAM space
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access.
Table 6.3
Module to be Accessed
DMAC registers
MCU operating mode, clock pulse
generator, power-down control, interrupt
controller, and bus controller registers
I/O port PFCR registers and WDT registers 2Pφ
TPU, PPG, SCI, and A/D registers and I/O
port registers other than PFCR
HCAN registers
SSU registers
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Number of Access Cycles for On-Chip Memory Spaces
Number of Access Cycles for Registers of On-Chip Peripheral Modules
Access
Read
Read
Write
Number of Cycles
Read Write
2Iφ
2Iφ 3Iφ
3Pφ
2Pφ
4Pφ
3Pφ
Section 6 Bus Controller (BSC)
Number of Access Cycles
One Iφ cycle
One Iφ cycle
Two Iφ cycles
Write Data Buffer Function
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Rev. 3.00 Mar. 14, 2006 Page 129 of 804
REJ09B0104-0300