Figure 12.14 Access Timing For Mpx Space (Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1) - Renesas HD6417641 Hardware Manual

Section 12 Bus State Controller (BSC)
CKIO
A25 to A16
CS5B
RD/WR
AH
RD
Read
D7 to D0 or
D15 to D0
WEn
Write
D7 to D0 or
D15 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
(Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
Rev. 4.00 Sep. 14, 2005 Page 334 of 982
REJ09B0023-0400
Ta1 Tadw Ta2
Address
Address
Figure 12.14 Access Timing for MPX Space
Ta3 T1 Tw Twx T2
Data
Data