Operating Modes; External Address Space Read Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
17.5.5

Operating Modes

This module has two operating modes: external address space read mode and SPI operating mode.
In external address space read mode, a read access to the SPI multi I/O bus space is converted into SPI communication
and data is received. After data acquisition, data is returned to the bus master that is the issuing source. For details, see
section 17.5.6, External Address Space Read Mode.
In SPI operating mode, arbitrary SPI communication is carried out using register settings. For details, see section
17.5.8, SPI Operating Mode.
17.5.6

External Address Space Read Mode

A read access to the SPI multi I/O bus space can be converted into SPI communication in external address space read
mode. Further, the commands, optional commands, option data, and dummy cycle issued for reading can be modified
using registers.
For the address, option data, and read data, either SDR or DDR transfer can be selected using the appropriate register
when the SPBCLK frequency division ratio is two or larger (RZ/A1LU only).
In external address space read mode, either normal read operation or burst read operation can be selected. The transfer
format is determined based on the following registers.
- Common control register (CMNCR)
- SSL delay register (SSLDR)
- Bit rate setting register (SPBCR)
- Data read control register (DRCR)
- Data read command setting register (DRCMR)
- Data read extended address setting register (DREAR)
- Data read option setting register (DROPR)
- Data read enable setting register (DRENR)
- Data read dummy cycle setting register (DRDMCR).
- Data read DDR enable register (DRDRENR)*
Note: * RZ/A1LU only
(1) Normal Read Operation
When the RBE bit in DRCR is set to 0, normal read operation is performed.
In the normal read operation, the data of 8 bits, 16 bits, 32 bits, and 64 bits are read for respectively a byte, a word, and a
longword read access. Here, a byte access is enabled only when one serial flash memory is connected. After reading, the
SPBSSL pin is negated.
The normal read operation timing is shown in Figure 17.7.
t1 is the time period from SPBSSL pin assertion to SPBCLK oscillation (clock delay), t2 is the time period from
transmission of the last SPBCLK edge of a transfer to SPBSSL pin negation (SPBSSL negation delay), and t3 is the time
period from one transfer end to the next transfer start (next access). For details of t1, t2, and t3, see section 17.5.9,
Transfer Format.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
17. SPI Multi I/O Bus Controller
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