Internal Bus; Access To Internal Address Space - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.12

Internal Bus

6.12.1

Access to Internal Address Space

The internal address spaces of this LSI are the on-chip RAM space and register space for the on-
chip peripheral modules. The number of cycles necessary for access differs according the space.
Table 6.25 shows the number of access cycles for each on-chip memory space.
Table 6.25 Number of Access Cycles for On-Chip Memory Spaces
Access Space
On-chip RAM space
In access to the registers for on-chip peripheral modules, the number of access cycles differs
according to the register to be accessed. When the dividing ratio of the operating clock of a bus
master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0
to n-1 are inserted for register access in the same way as for external bus clock division.
The number of access cycles to the registers for on-chip peripheral modules is shown in table 6.26.
Table 6.26 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Module to be Accessed
MCU operating mode, clock pulse
generator, power-down control registers,
interrupt controller, bus controller, and DTC
registers
I/O port PFCR registers and WDT registers 2Pφ
I/O port registers other than PFCR, TPU,
PPG, TMR, SCI, A/D, and D/A registers
Rev.2.00 Jun. 28, 2007 Page 210 of 666
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Access
Read
Write
Number of Cycles
Read Write
2Iφ 3Iφ
3Pφ
2Pφ
Number of Access Cycles
One Iφ cycle
One Iφ cycle
Write Data Buffer Function
Disabled
Disabled
Enabled