Duty Adjustment Circuit; Medium-Speed Clock Divider; Bus Master Clock Selection Circuit - Renesas Hitachi H8S/2194 Series Hardware Manual

10.4

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
10.5

Medium-Speed Clock Divider

The medium-speed divider divides the system clock to generate φ/16, φ/32, and φ/64 clocks.
10.6

Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/16, φ/32 or φ/64) to be supplied to the bus master (CPU), according to the settings of
bits SCK2 to SCK0 in SBYCR.
Rev. 2.0, 11/00, page 231 of 1037