Duty Correction Circuit; Figure 26.6 Timing Of External Clock Output Stabilization Delay Time; Table 26.4 External Clock Output Stabilization Delay Time - Renesas H8S/2158 User Manual

Table 26.4 External Clock Output Stabilization Delay Time

Condition: V = 2.7 V to 3.6 V, AV
CC
Item
External clock output stabilization delay
time
includes a RES pulse width (t
Note: * t
DEXT
2.7 V
V
CC
V
STBY
IH
EXTAL
φ
(Internal and external)
RES
Note: * The external clock output stabilization delay time (t

Figure 26.6 Timing of External Clock Output Stabilization Delay Time

26.2

Duty Correction Circuit

The duty correction circuit is valid when the oscillating frequency is 5 MHz or more. It corrects
the duty of a clock that is output from the oscillator, and generates the system clock (φ).
= 2.7 V to 3.6 V, V
CC
Symbol Min.
t * 500
DEXT
).
RESW
t
*
DEXT
) includes a RES pulse width (t
DEXT
Rev. 3.00 Jan 25, 2006 page 765 of 872
Section 26 Clock Pulse Generator
= AV = 0 V
SS SS
Max. Unit
µs
—
RESW
REJ09B0286-0300
Remarks
Figure 26.6
).