Duty Adjustment Circuit; Medium-Speed Clock Divider; Bus Master Clock Selection Circuit - Renesas H8S Series Hardware Manual

Table 20-4 and figure 20-6 show the input conditions for the external clock.
Table 20-4 External Clock Input Conditions
Item
External clock input
low pulse width
External clock input
high pulse width
External clock rise time
External clock fall time
Clock low pulse width
level
Clock high pulse width
level
20.4

Duty Adjustment Circuit

When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal
from the oscillator to generate the system clock (ø).
20.5

Medium-Speed Clock Divider

The medium-speed clock divider divides the system clock to generate ø/2, ø/4, ø/8, ø/16, and ø/32.
20.6

Bus Master Clock Selection Circuit

The bus master clock selection circuit selects the system clock (ø) or one of the medium-speed clocks (ø/2, ø/4, or ø/8,
ø/16, and ø/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR.
V
CC
to 5.5 V
Symbol Min
t 40
EXL
t 40
EXH
t —
EXr
t —
EXf
t 0.4
CL
80
t 0.4
CH
80
EXTAL
t
EXr
Figure 20-6 External Clock Input Timing
= 5.0 V ±
= 2.7 V V
CC
10%
Max Min Max
— 20 —
— 20 —
10 — 5
10 — 5
0.6 0.4 0.6
— 80 —
0.6 0.4 0.6
— 80 —
t t
EXH EXL
t
EXf
Test
Unit Conditions
ns Figure 20-6
ns
ns
ns
ø ≥ 5 MHz
t Figure 22-4
cyc
ns ø < 5 MHz
ø ≥ 5 MHz
t
cyc
ns ø < 5 MHz
× 0.5
V
CC
Rev.6.00 Oct.28.2004 page 665 of 1016
REJ09B0138-0600H