EXTAL
V
CC
STBY
V
IH
EXTAL
φ (internal or
external)
RES
Figure 20.7 External Clock Output Settling Delay Timing
20.3
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the signal that becomes the system clock.
20.4
Prescalers
The prescalers divide the system clock (φ) to generate internal clocks (φ/2 to φ/4096).
t
EXH
t
EXr
Figure 20.6 External Clock Input Timing
t
DEXT
Section 20 Clock Pulse Generator
t
EXL
× 0.7
V
CC
0.3 V
t
EXf
Rev. 7.00 Sep 21, 2005 page 659 of 878
× 0.5
V
CC
REJ09B0259-0700