Duty Correction Circuit - Renesas H8S/2100 Series Hardware Manual

V
CC
EXTAL
φ
(Internal and external)
RES
Note: * The external clock output stabilization delay time (t
Figure 25.6 Timing of External Clock Output Stabilization Delay Time
25.2

Duty Correction Circuit

The duty correction circuit generates the system clock (φ) by correcting the duty of the clock
output from the oscillator.
3.0 V
Section 25 Clock Pulse Generator
t *
DEXT
) includes a RES pulse width (t
DEXT
Rev. 1.00 May 09, 2008 Page 805 of 954
).
RESW
REJ09B0462-0100