Table of Contents
Advertisement
6. ROM
Bit 0—Program Setup (PSU)*: Bit 0 prepares for a transition to program mode. Set this bit to 1
before setting the P bit in FLMCR1. (Do not set the SWE, ESU, EV, PV, E, or P bit at the same
time.)
Bit 0: PSU
Description
0
Program setup cleared
1
Program setup
[Setting condition]
When FWE = 1 and SWE = 1
Note: * Do not set multiple bits simultaneously.
Do not cut V
6.3.3
Erase Block Register (EBR)
Bit
Initial value
Read/Write
EBR is a register that specifies the flash memory erase area, block by block. Bits 6 to 0 of EBR are
read/write bits. EBR is initialized to H'00 by a reset, in standby mode, when a low level is input to
the FWE pin, and when a high level is input to the FWE pin while the SWE bit in FLMCR1 is
cleared to 0. When a bit in EBR is set to 1, the corresponding block can be erased. Other blocks
are erase-protected. As erasing is carried out on a block-by-block basis, only one bit in EBR
should be set at a time (more than one bit must not be set).
The flash memory block configuration is shown in table 6.4. To erase the entire flash memory,
individual blocks must be erased in succession.
Rev.3.00 Jul. 19, 2007 page 130 of 532
REJ09B0397-0300
while a bit is set.
CC
7
6
5
⎯
EB6
EB5
0
0
0
⎯
R/W
R/W
4
3
EB4
EB3
EB2
0
0
R/W
R/W
R/W
(initial value)
2
1
0
EB1
EB0
0
0
0
R/W
R/W
Advertisement
Table of Contents
