Erase Block Register (Ebr); Flash Memory Power Control Register (Flpwcr) - Renesas H8/38024 Hardware Manual

6.6.3

Erase Block Register (EBR)

Bit 7
—
Initial value 0
Read/Write —
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.6 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Table 6.6 Division of Blocks to Be Erased
EBR Bit Name
0 EB0
1 EB1
2 EB2
3 EB3
4 EB4
6.6.4

Flash Memory Power Control Register (FLPWCR)

Bit 7
PDWND
Initial value 0
Read/Write R/W
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
6 5
— — EB4
0 0
— — R/W
Block (Size)
EB0 (1 Kbyte)
EB1 (1 Kbyte)
EB2 (1 Kbyte)
EB3 (1 Kbyte)
EB4 (28 Kbytes)
6 5
— —
0 0
— —
4 3
EB3 EB2
0 0
R/W R/W
Address
H'0000 to H'03FF
H'0400 to H'07FF
H'0800 to H'0BFF
H'0C00 to H'0FFF
H'1000 to H'7FFF
4 3
— — —
0 0
— — —
Rev. 6.00, 08/04, page 159 of 628
2 1 0
EB1 EB0
0 0 0
R/W R/W
2 1 0
— —
0 0 0
— —