Erase Block Register 1 (Ebr1) - Renesas H8 Series Hardware Manual

8-bit single-chip microcomputer

Hide thumbs Also See for H8 Series:

Table of Contents

Erase Block Register 1 (EBR1)

EBR1 is an 8-bit register that specifies large flash-memory blocks for programming or erasure.

EBR1 is initialized to H'F0 upon reset, in sleep mode, subsleep mode, watch mode, and standby

mode, and when 12 V is not applied to FV

block is selected and can be programmed and erased. The erase block map is shown in figure 6.7,

and the correspondence between bits and erase blocks is shown in table 6.8.

Initial value

* Word access cannot be used on this register; byte access must be used. For

information on access to this register, see note 11 in section 6.9, Flash Memory

Programming and Erasing Precautions. LB3 is invalid in the H8/3643F, and LB3 and

LB2 are invalid in the H8/3642AF.

Bits 7 to 4    Reserved: Bits 7 to 4 are reserved; they are always read as 1, and cannot be

Bits 3 to 0    Large Block 3 to 0 (LB3 to LB0): These bits select large blocks (LB3 to LB0) to be

programmed and erased.

Bits 3 to 0:

Block LB3 to LB0 is not selected

Block LB3 to LB0 is selected

. When a bit in EBR1 is set to 1, the corresponding

Rev. 6.00 Sep 12, 2006 page 117 of 526

Section 6 ROM

(initial value)

REJ09B0326-0600