Erase Block Register 1 (Ebr1) - Renesas H8S/2633 Series Hardware Manual

Bit 7—Flash Memory Error (FLER): Indicates that an error has occurred during an operation on
flash memory (programming or erasing). When FLER is set to 1, flash memory goes to the error-
protection state.
Bit 7
FLER Description
0 Flash memory is operating normally
Flash memory program/erase protection (error protection) is disabled
[Clearing condition]
Power-on reset or hardware standby mode
1 An error has occurred during flash memory programming/erasing
Flash memory program/erase protection (error protection) is enabled
[Setting condition]
See section 22.8.3, Error Protection
Bits 6 to 0—Reserved: These bits always read 0.
22.5.3

Erase Block Register 1 (EBR1)

Bit:
Initial value:
R/W:
EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a power-on reset, in hardware standby mode and software standby mode,
when a low level is input to the FWE pin, and when a high level is input to the FWE pin and the
SWE1 bit in FLMCR1 is not set. When a bit in EBR1 is set to 1, the corresponding block can be
erased. Other blocks are erase-protected. Only one of the bits of EBR1 and EBR2 combined can
be set. Do not set more than one bit, as this will cause all the bits in both EBR1 and EBR2 to be
automatically cleared to 0. When on-chip flash memory is disabled, a read will return H'00, and
writes are invalid.
The flash memory erase block configuration is shown in table 22-7.
7 6 5
EB7 EB6 EB5
0 0 0
R/W R/W R/W
4 3 2
EB4 EB3 EB2
0 0 0
R/W R/W R/W
(Initial value)
1 0
EB1 EB0
0 0
R/W R/W
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