Flash Memory Control Register 2 (Flmcr2); Erase Block Register (Ebr) - Renesas H8/3847R Series Hardware Manual

Section 6 ROM
6.6.2

Flash Memory Control Register 2 (FLMCR2)

Bit 7
FLER
Initial value 0
Read/Write R
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER)
This bit is set when the flash memory detects an error and goes to the error-protection state during
programming or erasing to the flash memory. See section 6.9.3, Error Protection, for details.
Bit 7
FLER Description
0 The flash memory operates normally.
1 Indicates that an error has occurred during an operation on flash memory
(programming or erasing).
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.6.3

Erase Block Register (EBR)

Bit 7
EB7
Initial value 0
Read/Write R/W
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.7 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Rev. 6.00 Aug 04, 2006 page 174 of 680
REJ09B0145-0600
6 5
— —
0 0
— —
6 5
EB6 EB5 EB4
0 0
R/W R/W R/W
4 3
— — —
0 0
— — —
4 3
EB3 EB2
0 0
R/W R/W
2 1 0
— —
0 0 0
— —
(initial value)
2 1 0
EB1 EB0
0 0 0
R/W R/W