Tpc Output Control Register (Tpcr) - Renesas F-ZTAT H8 Series Hardware Manual

11.2.9

TPC Output Control Register (TPCR)

TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit 7
G3CMS1
Initial value 1
Read/Write R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP to TP )
15
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits
select the compare match event that triggers TPC output group 3 (TP
Bit 7: G3CMS1 Bit 6: G3CMS0
0 0
1
1 0
1
6 5
G3CMS0 G2CMS1
1 1
R/W R/W
Group 2 compare
match select 1 and 0
These bits select
12
the compare match
event that triggers
TPC output group 2
(TP to TP )
11
Description
TPC output group 3 (TP
match in ITU channel 0
TPC output group 3 (TP
match in ITU channel 1
TPC output group 3 (TP
match in ITU channel 2
TPC output group 3 (TP
match in ITU channel 3
Section 11 Programmable Timing Pattern Controller
4 3
G2CMS0 G1CMS1
1 1
R/W R/W
Group 1 compare
match select 1 and 0
These bits select
8
the compare match
event that triggers
TPC output group 1
(TP to TP )
7 4
to TP
15
to TP
15
to TP
15
to TP
15
Rev. 3.00 Mar 21, 2006 page 409 of 814
2 1
G1CMS0 G0CMS1 G0CMS0
1 1
R/W R/W
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP to TP )
3 0
to TP ).
15 12
) is triggered by compare
12
) is triggered by compare
12
) is triggered by compare
12
) is triggered by compare
12
(Initial value)
REJ09B0302-0300
0
1
R/W