Pwm Clock Control Register (Pwmckcr); Pwm Output Control Register B (Pwmoutcr) - Renesas H8S/2100 Series Hardware Manual

Section 9 8-Bit PWM Timer (PWMU)
9.3.1

PWM Clock Control Register (PWMCKCR)

PWMCKCR selects the PWM clock source.
Bit Bit Name
7, 6 CLK1, CLK0 All 0

5 to 0
9.3.2

PWM Output Control Register B (PWMOUTCR)

PWMOUTCR controls enabling and disabling of the PWM output and counter operation of each
channel.
Bit Bit Name
7 CNTMD45B
Rev. 1.00 May 09, 2008 Page 202 of 954
REJ09B0462-0100
Initial
Value R/W
R/W
All 0 R
Initial
Value R/W
0 R/W
Description
Clock Select 1, 0
These bits select the PWM count clock source.
CLK1 CLK0
0: Internal clock φ is selected
0
1: Internal clock φ/2 is selected
0
0: Internal clock φ/4 is selected
1
1: Internal clock φ/8 is selected
1
Reserved
These bits are always read as 0 and cannot be
modified.
Description
Channel 4 and 5, 12-bit Counter Select
0: Channel 4 and 5 are set to 8-bit count operating
mode
1: Channel 4 and 5 are set to 12-bit count operating
mode
When selecting 12-bit count operating mode, 16-bit
count mode must be non-selectable (CNTMD45A =
0). For details, see table 9.5.