Ppg Output Control Register (Pcr) - Renesas H8S/2368 Series Hardware Manual

Bit Bit Name
7 —
to
4
3 NDR3
2 NDR2
1 NDR1
0 NDR0
11.3.4

PPG Output Control Register (PCR)

PCR selects output trigger signals on a group-by-group basis. For details on output trigger
selection, refer to section 11.3.5, PPG Output Mode Register (PMR).
Bit Bit Name
7 G3CMS1
6 G3CMS0
5 G2CMS1
4
G2CMS0
3 G1CMS1
2 G1CMS0
Rev. 2.00, 05/03, page 460 of 820
Initial Value R/W
1 —
0 R/W
0 R/W
0 R/W
0 R/W
Initial Value R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
Description
Reserved
These bits are always read as 1 and cannot be
modified.
Next Data Register 3 to 0
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Description
Group 3 Compare Match Select 1 and 0
Select output trigger of pulse output group 3.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
Group 2 Compare Match Select 1 and 0
Select output trigger of pulse output group 2.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
Group 1 Compare Match Select 1 and 0
Select output trigger of pulse output group 1.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3