Ppg Output Control Register (Pcr) - Renesas H8S Series Hardware Manual

Address H'FF4D
Bit : 7
NDR7
Initial value : 0
R/W : R/W
Address H'FF4F
Bit : 7
—
Initial value : 1
R/W : —
11.2.5

PPG Output Control Register (PCR)

Bit : 7
G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0
Initial value : 1
R/W : R/W
PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a group-by-group basis.
PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode.
Bits 7 and 6—Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match
that triggers pulse output group 3 (pins PO15 to PO12).
Bit 7
G3CMS1
0
1
Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match
that triggers pulse output group 2 (pins PO11 to PO8).
Bit 5
G2CMS1
0
1
Rev.6.00 Oct.28.2004 page 418 of 1016
REJ09B0138-0600H
6 5
NDR6 NDR5 NDR4
0 0
R/W R/W R/W
6 5
— —
1 1
— —
6 5
1 1
R/W R/W R/W
Description
Bit 6
G3CMS0 Output Trigger for Pulse Output Group 3
0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
0 Compare match in TPU channel 2
1 Compare match in TPU channel 3
Description
Bit 4
G2CMS0 Output Trigger for Pulse Output Group 2
0 Compare match in TPU channel 0
1 Compare match in TPU channel 1
0 Compare match in TPU channel 2
1 Compare match in TPU channel 3
4 3 2
— —
0 1 1
— —
4 3 2
— NDR3 NDR2
1 0 0
— R/W R/W
4 3 2
1 1 1
R/W R/W
1 0
— —
1 1
— —
1 0
NDR1 NDR0
0 0
R/W R/W
1 0
1 1
R/W R/W
(Initial value)
(Initial value)