Table 5.7 Cpu Priority Control; Table 5.8 Example Of Priority Control Function Setting And Control State - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer

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CPU Priority Control

Table 5.8 shows an setting example of the priority control function over the DMAC and the

transfer request control state. Although the DMAC priority levels can be assigned for each

channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be

performed independently by assigning the different priority levels.

Example of Priority Control Function Setting and Control State

Interrupt Control

Control Status

CPUP2 to CPUP0

B'111 to B'000

B'111 to B'000

Transfer Request Control State

Rev. 3.00 Mar. 14, 2006 Page 121 of 804

Section 5 Interrupt Controller

Updating of CPUP2

REJ09B0104-0300

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