Precharge State Control; Wait Control - Renesas H8S Series Hardware Manual

6.5.7

Precharge State Control

When DRAM is accessed, RAS precharging time must be secured. With the H8S/2357 Series, one T
inserted when DRAM space is accessed. This can be changed to two T
appropriate number of T
Figure 6-16 shows the timing when two T
When the TPC bit is set to 1, two T
Read
Write
Note: n = 2 to 5
6.5.8

Wait Control

There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using
the WAIT pin.
Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from
0 to 3 wait states can be inserted automatically between the T
WCRL.
Pin Wait Insertion: When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled
regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first
inserted. If the WAIT pin is low at the falling edge of ø in the last T
pin is held low, T states are inserted until it goes high.
w
cycles according to the DRAM connected and the operating frequency of the H8S/2357 Group.
p
states are inserted.
p
states are also used for refresh cycles.
p
T
p1
ø
A to A
23 0
CSn, (RAS)
CAS, LCAS
HWR, (WE)
D to D
15 0
HWR, (WE)
D to D
15 0
Figure 6-16 Timing with Two Precharge States
states by setting the TPC bit in MCR to 1. Set the
p
T T
p2 r
Row
state and T state, according to the settings of WCRH and
c1 c2
or T state, another T
c1 w
state is always
p
T T
c1 c2
Column
state is inserted. If the WAIT
w
Rev.6.00 Oct.28.2004 page 141 of 1016
REJ09B0138-0600H