Access State Control Register (Astcr) - Renesas H8SX/1650 Hardware Manual

Section 6 Bus Controller (BSC)
6.2.2

Access State Control Register (ASTCR)

ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space and enables/disables wait cycle insertion.
Bit 15
Bit Name AST7
Initial Value 1
R/W R/W
Bit 7

Bit Name
Initial Value 0
R/W R
Bit Bit Name
15 AST7
14 AST6
13 AST5
12 AST4
11 AST3
10 AST2
9 AST1
8 AST0

7 to 0
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14 13
AST6 AST5
1 1
R/W R/W
6 5
 
0 0
R R
Initial
Value R/W Description
1 R/W Area 7 to 0 Access State Control
1 R/W These bits select whether the corresponding area is to be
designated as 2-state access space or 3-state access
1 R/W
space. Wait cycle insertion is enabled or disabled at the
1 R/W
same time.
1 R/W
0: Area n is designated as 2-state access space
1 R/W
1 R/W
1: Area n is designated as 3-state access space
1 R/W
(n = 7 to 0)
All 0 R Reserved
These are read-only bits and cannot be modified.
12 11
AST4 AST3
1 1
R/W R/W
4 3
 
0 0
R R
Wait cycle insertion in area n access is disabled
Wait cycle insertion in area n access is enabled
10 9
AST2 AST1
1 1
R/W R/W
2 1
 
0 0
R R
8
AST0
1
R/W
0

0
R