Precharge State Control; Figure 6.24 Example Of Timing With Two-State Precharge Cycle (Rast = 0, Cast = 0) - Renesas H8S/2368 Series Hardware Manual

6.6.8

Precharge State Control

When DRAM is accessed, a RAS precharge time must be secured. With this LSI, one T
always inserted when DRAM space is accessed. From one to four T
setting bits TPC1 and TPC0 in DRACCR. Set the optimum number of T
DRAM connected and the operating frequency of this LSI. Figure 6.24 shows the timing when
two T states are inserted. The setting of bits TPC1 and TPC0 is also valid for T
p
cycles.
Address bus
(
,
( )
( )
Read
Data bus
( )
Write
( )
Data bus
Note: n = 2, 3
Figure 6.24 Example of Timing with Two-State Precharge Cycle
T
p1
Row address
)
(RAST = 0, CAST = 0)
T T
p2 r
High
High
Rev. 2.00, 05/03, page 159 of 820
p
states can be selected by
p
cycles according to the
p
states in refresh
p
T T
c1 c2
Column address
state is