Table 5.7
Interrupt
Control
Interrupt
Mode
Priority
0
Default
2
IPR setting
Table 5.8 shows an setting example of the priority control function over the DMAC and the
transfer request control state. Although the DMAC priority levels can be assigned for each
channel, table 5.8 gives a single channel description. Thus, transfer for each channel can be
performed independently by assigning the different priority levels.
Table 5.8
Interrupt Control
Mode
0
2
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CPU Priority Control
Interrupt
Mask Bit
I = any
I = 0
I = 1
I2 to I0
Example of Priority Control Function Setting and Control State
CPUPCE in
CPUP2 to
CPUPCR
CPUP0
0
Any
1
B'000
B'100
B'100
B'100
B'000
0
Any
1
B'000
B'000
B'011
B'100
B'101
B'110
B'111
B'101
B'101
IPSETE in
CPUPCR
CPUP2 to CPUP0
0
B'111 to B'000
1
B'000
B'100
0
B'111 to B'000
1
I2 to I0
DMAP2 to
DMAP0
Any
B'000
B'000
B'011
B'101
B'101
Any
B'000
B'101
B'101
B'101
B'101
B'101
B'101
B'101
B'101
Section 5 Interrupt Controller
Control Status
Updating of CPUP2
to CPUP0
Enabled
Disabled
Enabled
Disabled
Transfer Request Control State
DMAC
Enabled
Enabled
Masked
Masked
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Masked
Masked
Enabled
Enabled
Rev. 3.00 Mar. 14, 2006 Page 121 of 804
REJ09B0104-0300