Access State Control Register (Astcr) - Renesas H8S/2319 series Hardware Manual

6.2.2

Access State Control Register (ASTCR)

Bit : 7
AST7
Initial value : 1
R/W : R/W
ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access
space or a 3-state access space.
ASTCR sets the number of access states for the external memory space. The number of access
states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR.
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0—Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is to be designated as a 2-state access space or a 3-state access space.
Wait state insertion is enabled or disabled at the same time.
Bit n
ASTn Description
0 Area n is designated for 2-state access
Wait state insertion in area n external space is disabled
1 Area n is designated for 3-state access
Wait state insertion in area n external space is enabled
Rev. 5.00, 12/03, page 144 of 1088
6 5
AST6 AST5 AST4
1 1
R/W R/W
4 3
AST3 AST2
1 1
R/W R/W R/W
2 1 0
AST1 AST0
1 1 1
R/W R/W
(Initial value)
(n = 7 to 0)