Interrupt Priority Registers A To K (Ipra To Iprk) - Renesas H8S/2319 series Hardware Manual

5.2.2

Interrupt Priority Registers A to K (IPRA to IPRK)

Bit : 7
—
Initial value : 0
R/W : —
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for
interrupts other than NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: Read-only bits, always read as 0.
Table 5-3 Correspondence between Interrupt Sources and IPR Settings
Register
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
IPRG
IPRH
IPRI
IPRJ
IPRK
Note: * Reserved bits.
6 5
IPR6 IPR5 IPR4
1 1
R/W R/W
6 to 4
IRQ0
IRQ2
IRQ3
IRQ6
IRQ7
Watchdog timer
— *
TPU channel 0
TPU channel 2
TPU channel 4
8-bit timer channel 0
— *
SCI channel 1
4 3
— IPR2
1 0
R/W — R/W
Bits
2 to 0
IRQ1
IRQ4
IRQ5
DTC
— *
A/D converter
TPU channel 1
TPU channel 3
TPU channel 5
8-bit timer channel 1
SCI channel 0
— *
Rev. 5.00, 12/03, page 113 of 1088
2 1 0
IPR1 IPR0
1 1 1
R/W R/W