Interrupt Priority Registers A To K (Ipra To Iprk) - Renesas H8S Series Hardware Manual

Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes
for the interrupt controller.
Bit 5 Bit 4
INTM1 INTM0
0 0
1
1 0
1
Bit 3—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 3
NMIEG
0
1
5.2.2

Interrupt Priority Registers A to K (IPRA to IPRK)

Bit : 7
—
Initial value : 0
R/W : —
The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than
NMI.
The correspondence between IPR settings and interrupt sources is shown in table 5-3.
The IPR registers set a priority (levels 7 to 0) for each interrupt source other than NMI.
The IPR registers are initialized to H'77 by a reset and in hardware standby mode.
Bits 7 and 3—Reserved: These bits cannot be modified and are always read as 0.
Rev.6.00 Oct.28.2004 page 84 of 1016
REJ09B0138-0600H
Interrupt
Control Mode
0
—
2
—
Description
Interrupt request generated at falling edge of NMI input
Interrupt request generated at rising edge of NMI input
6 5
IPR6 IPR5
1 1
R/W R/W
Description
Interrupts are controlled by I bit
Setting prohibited
Interrupts are controlled by bits I2 to I0, and IPR
Setting prohibited
4 3 2
IPR4 — IPR2
1 0 1
R/W — R/W
(Initial value)
(Initial value)
1 0
IPR1 IPR0
1 1
R/W R/W